First device in the Speedster family embeds 20 lanes of 10.3 Gbps SerDes and four independent 1066 Mbps DDR2/DDR3 controllers.
Speedster uses familiar LUT-based fabric and standard synthesis and simulation tools so designers can use their existing RTL.
Signaling a breakthrough in three decades of field-programmable gate array design where performance has been sacrificed for flexibility and time-to-market, Achronix Semiconductor today announced that it has already begun shipping the world’s fastest FPGAs. The Speedster family, with the SPD60 as its initial member, delivers speeds up to 1.5 GHz, which represents a three-fold increase in performance over existing FPGAs.
Achronix early engagement customers have already found success with Speedster in applications requiring ASIC-like performance namely networking, telecommunications, test and measurement, encryption and other high-performance applications. These types of applications are an ideal fit for the Speedster family of FPGAs.
Achronix has partnered with leading synthesis vendors to make industry-standard tools and methodologies compatible with the Speedster family. Designers can leverage their existing Verilog and VHDL designs. The Achronix CAD environment supports both Synopsys Synplify Pro and Mentor Graphics’ Precision Synthesis tools for RTL synthesis. In addition, the Achronix CAD environment provides the necessary tools for physical implementation, performance optimization, timing analysis, simulation, debug, and device programming.
The Speedster family of FPGAs uses the Achronix patented picoPIPE acceleration technology that speeds the way data moves through the FPGA fabric. In the absence of a global clock, picoPIPEs use simple handshake protocols to efficiently control data flow, resulting in significantly improved performance, all along using standard RTL for design-entry and employing familiar FPGA tools. By coupling this innovative technology with a 10.3 Gbps serializer/deserializer to facilitate high system throughput and integrated DDR2/DDR3 controllers for high-speed memory interface, the Speedster family provides the I/O speed to match its outstanding core performance. The device is manufactured in TSMC’s high performance 65 nm G+ CMOS process.
Vinod /ITvoir network